VLSI Design > Functional Verification
Functional Verification is one of the major thrust areas of Masamb in which the expertise includes Transaction level modeling, Coverage driven Verification, Random Constraints Stimuli, Assertion based Verification using SystemC and SystemVerilog. The services in verification have ranged from best use of Verification Tools to SoC Verification and have involved debugging techniques, Assertion Modeling, Functional Coverage modeling, and Sequence Generation. The Verification IPs developed/ being developed is being implemented in both SystemVerilog and SystemC. The System Verilog IPs are being made available on OVM, VMM as well as Masamb's methodologies while the SystemC IPs are being made available using OSCI SystemC TLM-2.0. Masamb in a member of MIPI forum and is involved in developing complex Verification IPs based around the MIPI specification.

The Functional Verification expertise involves working on the following:
LANGUAGE