Masamb's expertise in Low Power Design Implementation encompasses CPF/UPF based low power flows/methodologies from front-end to the back-end. The core-skills include RTL Synthesis, Timing Analysis, DFT, Formal Verification, Physical Design Closure (Floorplanning, Clock Tree Synthesis, P&R, Timing, Noise, Powe & IR-Drop/Electromigration Analysis and Physical Verification). Besides, the team has good experience in applying various low power design techniques like MSMV, Power-shut-off, DVFS etc. The services in Design Implementation encompass complete RTL to GDSII implementation in Synopsys, Cadence and Magma flows in 32nm, 45nm, 65nm, 90nm, 130nm. Masamb has credentials in working on Physical Design expertise across complex blocks and has experience with MMMC timing closure on flat as well as hierarchical designs.

On the DFT side we have handled situation encountered in moving from higher to lower nodes, this includes AC Scan, and Scan compression DFT techniques. We have implemented low-power design techniques including clock gating, multi-VT, power islands & voltage islands. In addition Design Implementation team also has knowledge of CPU Architecture and RISC Processes